The present invention relates to interrupt handlers and, more particularly, to interrupt handlers for processors having the capability of executing instructions out-of-order.
In the field of data processing, when multiple instructions are executed or issued concurrently within a given machine cycle, throughput is enhanced by the use of multiple functional units. An exemplary system for issuing multiple instructions concurrently is shown and described in the aforementioned U.S. Pat. No. 4,807,115, herein incorporated by reference. This positive effect on throughout due to issuing multiple instructions is improved to an even greater degree when instructions are issued nonsequentially.
Of course, to sustain multiple instruction issuances per machine cycle, the data path must be widened to carry more than one instruction at a time.
All processors are expected to handle interrupts promptly and efficiently. The three basic interrupt types encountered by processors are external interrupts, exception traps and software traps.
External interrupts are generated from or by the environment (i.e., from process control, transaction processing, a process time-out, a printer, a terminal or the like).
Exception traps are generated by occurrences of certain events in the system (i.e., divide by zero, overflow or illegal operations). In general, these traps require a program abort, and indicate a program error or a machine malfunction. In some cases, these traps are used as conditional processing. Therefore, an interrupt handler is written for each specific situation.
Software traps are instruction-initiated interrupt requests. These traps provide a basis for controlling certain software applications.
When an interrupt request is received, the processor must save its processor state precisely, then load and execute an appropriate interrupt handler. Upon completion of the interrupt handling routine, the saved processor state is restored and the interrupted process can then resume.
From the foregoing discussion, it is clear that a processor state should contain enough information so that the interrupted process can be restarted, preferably at the precise point where it was interrupted. To be able to resume an interrupted process, the processor state should include the contents of the general purpose registers, the program counter, the condition register, all index registers and the main memory.
Conventionally, in order to identify the point at which a process is interrupted, the address of a specific instruction, say instruction I, is saved when the processor state is saved. All instructions that precede instruction I have been executed, while instruction I and those following it have not been executed. Instruction I thus provides a precise interrupt point.
Due to the very nature of multiple instruction execution, however, two or more instructions at different stages of execution may be interrupted. It is thus an ongoing and particularly vexing problem to handle an interruption while retaining the benefits of calculations that have been completed. Although multiple interrupts may be received at the same time, they must be prioritized and handled one at a time, even though the interrupt handler itself may be interrupted.
As hereinabove mentioned, conventionally the specific instruction at which processing is temporarily halted is pinpointed. This is called a precise interrupt. Unfortunately, such a simplistic interrupt mechanism is not suitable for use with an out-of-order execution machine. Since instructions issued may not be contiguous in an out-of-order execution machine, a conventional interrupt handling mechanism simply will not be appropriate.
The Model No. 6600 system manufactured by Control Data Corp. maintains a scratch pad or "SCOREBOARD" to resolve dependency conflicts among instructions in an instruction stream, and to allow these instructions to complete out-of-order. The so-called "exchange jump" is the mechanism by which the CPU handles interrupts. If the exchange jump sequence is requested, the CPU is permitted to issue instructions up to, but not including, the next instruction word. All issued instructions are allowed to run to completion. The CPU registers are then interchanged with the data stored in the exchange package. The CPU is restarted at the location specified by the new contents of the program address register. Since the machine must wait for two instructions to be issued and completed before the interrupt can be serviced, on average this approach exacts a penalty in latency (the time between receiving an interrupt request and saving the processor state).
In the Model No. 360/91 system manufactured by IBM Corp., reservation stations and a common data bus (CDB) are employed to enhance performance. Upon receipt of a precise interrupt request or a trap, instruction decoding is temporarily halted and all issued instructions are allowed to complete, thereby resulting in considerable latency. If an imprecise interrupt is generated via internal processing, the state of the system is lost, in which case the system cannot be properly restarted.
In the case of the Model No. CRAY-1 system manufactured by Cray Research, Inc., when an interrupt is received, instruction issue is temporarily terminated and all vector and memory bank references are allowed to complete. The interrupt handler is loaded and executed in a similar manner to that employed by the aforementioned CDC Model No. 6600 system. The CRAY-1 processor must wait for two instructions to complete, on average, before the processor state can be saved. However, as the CRAY-1 processor supports complex vector operations, the latency (in cycles) between receipt of the interrupt request and subsequent exception processing may be longer than that of the CDC 6600 processor.
More recently, machines which allow out-of-order instruction issuance, concurrent execution and out-of-order instruction completion have been proposed. In the High Performance Substrate (HPS) system, the dynamic instruction stream is used to maintain a data dependency graph derived from an instruction window. Instructions are scheduled in a sequential manner and retired serially at a maximum rate of one per cycle. In order to respond to interrupt requests, checkpointing has been proposed to allow precise interrupt handling. The checkpoints are used to divide the sequential instruction stream into smaller units to reduce the cost of "repair". A minimum of two checkpoints and hence two additional states are required.
The foregoing approach degrades the performance of the system, both in processor speed and in the time required to restore to a consistent processor state upon receiving an interrupt request. The speed of the system, and thus its performance, is slowed down by the movement of state information as the states change, and by the additional read instructions which must precede all instructions that alter the memory. The memory must be adjusted to a consistent state every time an interrupt request is received.
One of the simplest precise interrupt mechanisms is the in-order instruction completion method, as discussed in "Implementing Precise Interrupts in Pipelined Processors" by J. E. Smith and A. R. Pleszkun, IEEE Trans. Computer, vol. C-37, no. 5, pp. 562-573 (May 1988). An instruction is allowed to modify the process state when all preceding instructions are certain to be allowed to complete. A reorder buffer is added so that instructions are permitted to complete out-of-order. Instructions are reordered before they are permitted to modify the process state. History buffer and future files can reduce performance degradation, but the additional registers and their requisite data paths impose added cost and exact a performance penalty.
It would be advantageous to provide a system for handling interruptions of a machine capable of processing out-of-order instructions.
It would be advantageous to provide a system for interrupt handling in a machine that processes two or more instructions concurrently.
It would also be advantageous to retain computations performed for each instruction of a group of instructions, executed concurrently, when the processor is interrupted while instructions are being issued out-of-order.
It would also be advantageous to be able to interrupt vector operations without losing any results obtained, or corrupting the calculations.
It would also be advantageous to restart a vector operation at the completion of the interrupt handling sequence.
It would also be advantageous to provide such a system having the attributes of short latency and relative simplicity.